Simple generators.

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Simple test generators.

Here are some simple HRPT generators, which can be used to test the HRPT decoder. (Note that the generator output of the decoder/generator can't be used, because the FPGA's are loaded either with the decoder's program OR generator's program!)

It is ment to check that the PLL gets locked and the decoder gets in-sync.

The output is a split-phase signal. The data-content is a repeating frame-sync pattern: 60 sync-bits repeating every 63 cycles. After 1109 bits the sequence starts again; 100 sequences makes exactly 1 HRPT-frame.
The picture will show as a more or less random pattern of vertical bars with different grey values.

Generator
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HRPT 1

HRPT 2

HRPT/PDUS/any generator .

This is a more common generator. By loading the EPROM with the desired pattern a HRPT or PDUS signal can be generated.

For HRPT the 4060 should oscillate at about 21.28 MHz. This gives 1330 kHz at pin 7, which is needed to generate the split-phase signal (2x HRPT bit-frequency=665 kHz).
NOTE: Coil should be 3 uH!

For PDUS you need a 166.66x2=333.33 kHz output of the 4060. You can:

Use coil of about 3 uH (21.28 MHz) in combination with pin 4 OR
Use coil of about 48 uH (5.32 MHz) in combination with pin 7 OR
Use coil of 12 uH (10.64 MHz) in combination with pin 5; in this case you may replace the coil by a ceramic filter of 10.7 MHz to get a stable clock.

I have never tested the HRPT-pattern generation, but PDUS works. For PDUS you don't need the 74HCT153 and the last 74HCT163.

For this pattern you need a 333.33 kHz output of the 4060.
Connect PDUS_RES with RESET and use PDUS_OUT.

Download EPROM content for PDUS pattern generation: pduspat.bin (5824 bytes)
(explanation file size: 1 frame has 364 bytes, each bit of a byte needs 1 EPROM-byte, so 364x8 = 2912; for split-phase: x2 = 5824 bytes).

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Simple test generators.

Generator

schema

print

HRPT/PDUS/any generator .

Schema HRPT generator